1. Field of the Invention
The present invention relates to a semiconductor device having a circuit for adjusting the capacitance in an input/output terminal.
2. Description of the Prior Art
In recent years, in order to increase the operating frequency in a semiconductor device, not only improvement in an packing technique in an integrated circuit chip but also improvement in a technique of mounting the integrated circuit chip onto a package are also important objects. For example, a case of transmitting data from a first semiconductor device to a second semiconductor device via a data bus of 32 bits and a clock signal line on a 1 GHz clock is assumed. When it is assumed that the cycle of one clock is 1 ns and the second semiconductor device captures data at the leading edge of a clock signal, data has to arrive at the second semiconductor device at least about 0.2 ns before. This requirement is called setup time. Even one bit out of the 32-bit data is late, that is, when the setup time is not satisfied, accurate data transfer cannot be performed. Consequently, the requirement of the setup time has to be satisfied with respect to all of the 32-bit data.
In the case of transmitting data from the first semiconductor device to the second semiconductor device, according to wiring resistance of a wire connecting the semiconductor devices and the capacitance for input/output terminals of the first and second semiconductor devices, data arrival time largely differs. In the case of a semiconductor device which operates at high frequencies of hundreds MHz to a few GHz, for example, the input capacitance in an external input/output terminal in a packed state is subject to strong constraints. The capacitance of the input/output terminal is not only reduced but, in some cases, has to be controlled within a range from a predetermined value and a value less than a value obtained by adding 1 pF to the predetermined value.
In a semiconductor device such as a storage, there are cases such that variation in capacitance among a plurality of signal lines in a data bus or the like has to be suppressed to a few hundredths pF. The capacitance of the external input/output terminal is determined by the input capacitance in an input/output device external pin (bonding pad or the like) of the integrated circuit chip in the package and the capacitance of a wire extending from the device external pin to the external input/output terminal of the package. It is therefore necessary to control the capacitance of the device external pin in consideration of the wiring in the package.
Further, in order to increase the packing density, the user of the semiconductor device sometimes wires a common data bus on both the surface and back of a single circuit substrate and mount a plurality of semiconductor devices. When semiconductor devices having the same pin arrangement are mounted on the surface and the back of the circuit substrate, since the wiring pattern on the surface and that on the back are largely different from each other, it is difficult to design the wiring patterns and it takes time to design the patterns. Further, when signals are simultaneously supplied to both terminals A and D (FIG. 13) of a semiconductor device via wiring patterns on the surface and back of the same pin assignment, on the surface, the signal arrives at the terminal A and after that the signal arrives at the terminal D. On the contrary, on the back, the signal arrives at the terminal D and after that the signal arrives at the terminal A. In the semiconductor device which operates at very high speed, even the slight difference disturbs normal capture of the signal.
In order to avoid this, either terminal arrangement of a semiconductor device, pin assignment and mirror-symmetrical terminal arrangement, or a semiconductor device having pin assignment is necessary. By mounting semiconductor devices having a mirror symmetrical relation on the surface and back of the circuit substrate, a signal arrives at the terminal D after the signal arrives at the terminal A on both of the surface and back face and a screw is not easily caused.
FIGS. 13A and 13B are perspective views showing an example of wiring in a package adopting a BGA (Ball Grid Array) as one of CSPs (Chip Size Packages) as a package. FIGS. 13A and 13B show wiring states in packages when the pin arrays of the packages are made different symmetrically from each other by using the same integrated circuit chips. In FIG. 13A, a plurality of solder balls 201 are arranged on the back of a package substrate 200a. On the surface of the substrate 200a, an integrated circuit chip of the same size as that of the substrate 200a is mounted. Device external pins (pads) 202 of the integrated circuit chip are connected to the solder balls 201 on the back of the substrate via a plurality of wires 203a, 203b, 203c, 203d, 203e, . . . .
On the other hand, in FIG. 13B, the plurality of solder balls 201 on the back of a package substrate 200b are connected to the plurality of pads 202 on the surface of the substrate via a plurality of wires 204a, 204b, 204c, 204d, 204e, . . . .
In FIGS. 13A and 13B, only a part of the wires is shown and the other part is omitted. The positions of the device external pins on the integrated circuit chip are deviated to the lower side of the drawing and the intervals of the device external pins are irregular. The device external pins are therefore arranged asymmetrical with resect to the solder balls 201.
In the pin array shown in FIG. 13A, with respect to external terminals A, B and C (upper left) and terminals D and E (lower left) of the package, the solder balls 201 for the respective terminals are connected to the corresponding device external pins on the integrated circuit chip via the wires 203a, 203b, 203c, 203d, and 203e. In the following description, this will be called first pin assignment.
On the other hand, in the substrate 200b of FIG. 13B in which pins are assigned symmetrical with those in the substrate 200a, terminals A, B and C (lower left) are wired to the corresponding device external pins on the integrated circuit chip by the wires 204a, 204b and 204c shorter than the wires 203a, 203b and 203c, respectively. Terminals D and E (upper left) are wired by the wires 204d and 204e longer than the wires 203d and 203e. As shown in the example, even if the same chip is used and the package shape is the same, when the terminal array or pin assignment is different, the capacitance has to be adjusted in consideration of a difference in the wiring state due to the different terminal arrangement or pin assignment.
Conventional methods for adjusting the capacitance of an external pin include a method of providing a capacitor capable of changing the capacitance by an application voltage on an integrated circuit chip and adjusting the voltage applied to the capacitance, thereby adjusting output delay time (refer to, for example, Japanese Unexamined Patent Application No. 61-187356) and a method of connecting a capacitor provided on an integrated circuit chip to an output pin via a semiconductor switch and selecting an on/off state of the switch, thereby changing the capacitance value (refer to, for example, Japanese Unexamined Patent Application No. 63-246916).
In such conventional methods, however, in order to integrate a capacitor capable of varying the capacitance onto the same device, it is necessary to add a dedicated diffusion process or change the fabricating process itself. Since the device output pin and the capacitor for adjustment are connected to each other via a semiconductor switch, there is a problem such that adjustment of an input/output impedance is difficult when the circuit is an RF circuit due to an influence of parasite resistance, parasite capacitance, and the like caused by the semiconductor switch.
As one of circuits for adjusting capacitance to solve the problem of the conventional method, a circuit as shown in FIG. 14 can be mentioned. FIG. 14 is a circuit diagram showing a circuit configuration corresponding to one of a plurality of input/output device external pins (pads) in a semiconductor integrated device. An output circuit 302 as a buffer circuit for an output and an input circuit 303 as a buffer circuit for an input are connected to an input/output device external pin 301 via an aluminum wire 306 on the integrated circuit. The gate terminal of an n-channel MOS (Metal-Oxide Semiconductor) transistor 305 is disposed connectably to the input/output device external pin 301 via a switch 304. The drain and source terminals of the MOS transistor 305 are connected to the ground.
By the switch 304, the aluminum wire can be connected or interrupted. For example, every manufacturing lot, in the case of adding capacitance, by using a wiring mask of wiring in a state where the contact of the switch 304 is closed, the aluminum wire is formed at the contact of the switch on the integrated circuit. On the other hand, in the case of adding no capacitance, by using a wiring mask which does not form an aluminium wire at the contact of the switch 304, the switch is opened. In the case of adding the capacitance, the capacitor realized by the MOS transistor 305 can be connected to the input/output device external pin 301 directly via a low-resistance metal wire without through the semiconductor switch. Since the capacitor is realized by the MOS transistor, it is unnecessary to add a dedicated process.
FIG. 15 roughly shows the process for fabricating the semiconductor device. A wafer fabricating process (401), a diffusion process (402) and a wafer test process (403) are performed. A semiconductor chip which has passed the wafer test is assembled in a predetermined package in an assembly process (404) and a final test is carried out (405). A semiconductor device which has passed the final test is shipped (406). The aluminium wire is formed in the diffusion process 402. That is, the capacitance adjustment by the presence or absence of the aluminium wire as shown in FIG. 14 is performed before the wafer test process 403. The circuit characteristics of the device can be measured in the wafer test process 403. The adjustment of the input/output terminal capacitance by either forming the aluminium wire or not to correct characteristic variation in fabricating places and variation in lots in the diffusion process is performed based on a fabrication record, result of the test (404 in FIG. 15) after assembly, and the like. It brings about a problem such that the management of the fabricating process is complicated.
In the case of fabricating a product having a form of two kinds of pin arrays as described by referring to FIG. 13, the work in the diffusion process 402, that is, which aluminum wiring mask is to be used is determined according to the array used. In this case, when the aluminium wiring method in the diffusion process 402 is selected according to the number of devices to be shipped (406) kind by kind of the pin arrays, the number of devices to be shipped and the number of products at the end of the diffusion process can be made coincide with each other. Since the number of days from the wafer test process 403 after the diffusion process 402 to the shipment 406 is, for example, a few weeks or so, a large change in the necessary quantity cannot be promptly dealt with or it is necessary to hold a number of stocks.
An object of the invention is to provide a high-speed processing semiconductor device capable of easily managing and adjusting the capacitance of an input/output terminal.
According to the invention, a semiconductor device comprises: an external terminal; an internal circuit connected to the external terminal; a MOS transistor whose gate terminal is connected to the external terminal or whose drain and source have a common terminal connected to the external terminal; and a bonding pad for applying a predetermined voltage to a terminal which is not connected to the external terminal in the MOS transistor.